Parasitic Parameter Sensitivity Analysis and Simulation Evaluation Based on Cadence SKILL

Abstract

 Parasitic effects caused by interconnects have become increasingly critical in modern analog integrated circuits, especially as technology nodes in the semiconductor industry continue to advance. This paper presents an automated sensitivity analysis and simulation evaluation framework that addresses these challenges using Cadence SKILL and the Virtuoso platform. The purpose of this research is to identify and quantify the impact of interconnect parasitic parameters on circuit performance, enabling more efficient post-layout optimization. The proposed method incorporates automated parasitic insertion, simulation management, and statistical evaluation. Morris-based sensitivity analysis is used to determine the significance of individual parasitic elements, while a two-dimensional interaction analysis based on regression identifies pairs of critical variables with compensatory behavior. The experimental test case is a bandgap reference circuit implemented in TSMC 65nm technology, and key performance indicators such as gain, bandwidth, gain-bandwidth product, phase margin, and power supply rejection ratio are evaluated to comprehensively score the sensitivity indicators under various performance conditions. The results demonstrate that the proposed method can effectively identify critical parasitic parameters affecting the performance and maintain high simulation accuracy while significantly reducing complexity by ignoring low-sensitivity parameters. This research offers an efficient and scalable analysis approach for post-layout simulation modeling of analog circuits, showing strong potential for practical engineering applications.